FIG. 8 shows the configuration of a totem-pole-type load driving circuit appropriate for high-speed driving of a capacitive load. In FIG. 8, examples of the load shown as load electrostatic capacitance C.sub.L include power MOSFET, CCD, etc.
In the aforementioned conventional totem-pole-type load driving circuit, in order to make charge/discharge driving for load electrostatic capacitance C.sub.L, transistor TR.sub.1 connected to load electrostatic capacitance C.sub.L and transistor TR.sub.2 connected in the Darlington connection to transistor TR.sub.3 are turned ON alternately by means of Schottky barrier (SB) transistor TR.sub.4 as a phase splitter (for phase splitting).
When transistor TR.sub.2 is turned on while transistor TR.sub.1 is in the OFF state, charging is carried out from V.sub.CC power source to load electrostatic capacitance C.sub.L by transistor TR.sub.2 ; when transistor TR.sub.1 is turned ON while transistor TR.sub.2 is in the OFF state, discharging is carried out from load electrostatic capacitance C.sub.L to ground GND by transistor TR.sub.1.
The charging time to load electrostatic capacitance C.sub.L depends on the rise time t.sub.r defined by the time constant obtained from the pull-up resistance R.sub.UP, the sum of the resistance R of the resistor element LR connected to the collector of transistor TR.sub.2 and the equivalent resistance TR.sub.2 of transistor R.sub.TR2 and load electrostatic capacitance C.sub.L.
The discharging time from load electrostatic capacitance C.sub.L depends on drop time t.sub.d defined by the time constant defined by the pull-down resistance R.sub.LOW, the equivalent resistance R.sub.TR1 of transistor TR.sub.1 and load electrostatic capacitance C.sub.L.
A resistor element ER is connected to the base of transistor TR.sub.1 so that transistor TR.sub.1 can be turned off rapidly.
Recently, there is a demand on the totem-pole-type load driving circuit characterized in that even when a load as large as having a load electrostatic capacitance C.sub.L of 500-2000 pF or larger is to be driven, a delay time t.sub.pd as short as about 20-50 nsec can still be guaranteed. That is, there is a demand on the totem-pole-type load driving circuit with high-operational ability for a large capacitive load.
For this purpose, the aforementioned pull-up resistance R.sub.UP and the pull-down resistance R.sub.LOW have to be as small as several .OMEGA..
The totem-pole-type load driving circuit may have various applications. Depending on the application, the load may be switched from the use state to the no-load state, or the "0" load state may take place.
In order to form a high-speed circuit configuration for the totem-pole-type load driving circuit matched with large load electrostatic capacitance C.sub.L, the aforementioned pull-up resistance R.sub.UP and the pull-down resistance R.sub.LOW are made small. In this case, suppose the capacitive load enters the no-load state, or "0", the rise time t.sub.r becomes too short, the sustain voltage of the transistor is decreased, and breakdown phenomenon takes place, in which a large current flows through transistors TR.sub.1, TR.sub.2, and the transistors are damaged.
The aforementioned breakdown phenomenon may be analyzed with reference to FIG. 9. FIG. 9 shows the peripheral portion of transistor TR.sub.1 of the totem-pole-type load driving circuit shown in FIG. 8.
For the output transistor of the various types of driver devices, transistor TR.sub.1 in this example, when the output, namely, the potential of the collector rises at a high speed, the breakdown phenomenon may take place by a current flowing through Miller capacitance C.sub.M defined by base-collector parasitic capacitance C.sub.BC between collector C and base B times with gain G of the transistor. The critical voltage (output voltage) that determines whether the breakdown phenomenon takes place is called the "sustain voltage."
It is well known that the aforementioned breakdown phenomenon may take place due to the fast rise of the output voltage due to the reverse electromotive force of the inductive load. It also takes place for the capacitive load.
In the breakdown phenomenon, transistors TR.sub.1 and TR.sub.2 become primarily ON simultaneously. At the same time, the state in turing ON is repeated for several rounds in a vibrational state. In this case, the excessive current flows to transistor TR.sub.1, TR.sub.2, and these transistors TR.sub.1 and TR.sub.2 may be damaged in many cases.
As the burst current flowing into the transistor is high when load electrostatic capacitance C.sub.L is charged, it is impossible to adopt the method of setting a surge current protector circuit in the operation with the breakdown phenomenon, although it has been tried.
In order to prevent the breakdown phenomenon, it is necessary to increase the sustain voltage.
As a method to increase the sustain voltage, the base-open collector yield voltage BV.sub.CEO of transistor TR.sub.1 may be raised. However, in order to raise the base-open collector yield voltage BV.sub.CEO, the epitaxial layer of the transistor has to be made thicker.
However, when the epitaxial layer is made thicker, various problems take place, such as an increase in the size of the semiconductor substrate, increase in the dimensions of transistor elements. As the parasitic capacitance is increased, the delay time t.sub.pd becomes longer, the driving power becomes higher, and the power consumption is increased. Also, as the parasitic capacitance is increased, the Miller capacitance C.sub.M is increased, and it becomes impossible to perform the high-speed charging/discharging operation for load electrostatic capacitance C.sub.L. In addition, the dimensions of the IC chip are increased, and the price is also increased.
Consequently, an increase in the thickness of the epitaxial layer so as to increase the base-open collector yield voltage BV.sub.CEO and hence to increase the sustain voltage is not generally regarded as a satisfactory approach for increasing the sustain voltage.